The present invention relates generally to xe2x80x9cRotated Readxe2x80x9d register file memory structures and xe2x80x9cContent Addressable Memoryxe2x80x9d structures, and, more particularly, to a method and structure for preventing read corruption in xe2x80x9cRotated Readxe2x80x9d register file memory structures and xe2x80x9cContent Addressable Memoryxe2x80x9d structures.
As the performance of microprocessors and processing systems has continued to advance, more and more systems have begun to incorporate memory structures other than standard register files that read and write data on a row-by row basis. Two examples of memory structures that are not standard register files are xe2x80x9cRotated-Readxe2x80x9d register file memory structures and xe2x80x9cContent Addressable Memoryxe2x80x9d (CAM) arrays. In both rotated-read register file memory structures and CAM arrays data is read a column at a time across a given row rather than on a strictly row-by-row basis.
Using the column reads associated with rotated-read register file memory structures and CAM arrays it is possible, and often happens, that a read operation of a given memory cell can take place at the same time the row containing the memory cell is being written to and before the given cell has been written to. Consequently, two problems result.
The first problem that occurred when a column read operation took place at the same time a row was being written to was that the data read in this situation was incorrect or xe2x80x9cbadxe2x80x9d data. This xe2x80x9cbadxe2x80x9d data problem was easily corrected by methods and structures well known to those of skill in the art whereby the xe2x80x9cbadxe2x80x9d data was ignored and the correct data was read on the next read cycle. Consequently, from an architectural standpoint the xe2x80x9cbadxe2x80x9d data problem was a non-issue and a non-problem.
However, the second, and far more troublesome, problem that occurred when a column read operation took place at the same time a row was being written to was that the value being read was typically an unknown, or indeterminate, value that was neither a digital zero nor a digital one, i.e., the value read was between a digital low and a digital high. As noted above, from an architectural standpoint, this was a non-issue; the correct data was simply read on the next cycle. However, the indeterminate value read when a column read operation took place at the same time a row was being written to resulted in the indeterminate values being propagated down stream to the sensing elements, logic elements, or other downstream circuitry of the system and, since the indeterminate value was neither a digital low nor a digital high, the downstream circuitry often failed because the downstream circuits were designed to process signals consisting of either a digital low or a digital high but not an intermediate value. Consequently, the effects of the indeterminate value that resulted a column read operation took place at the same time a row was being written to on downstream circuitry was often circuit failure and it was found that correcting this problem in silicon was extremely difficult.
What is needed is a method and apparatus for preventing read corruption in rotated-read register file memory structures and CAM array structures by preventing indeterminate, or intermediate, values from being propagated to sensing elements, logic circuits, or other circuitry downstream from the memory structure and ensuring that the sensing elements, logic circuits, or other downstream circuitry receive only defined digital low or digital high signals.
The present invention is directed to a method and apparatus for preventing read corruption in rotated-read register file memory structures and CAM array structures by preventing indeterminate, or intermediate, values from being propagated to sensing elements, logic circuits, or other circuitry downstream from the memory structure and ensuring that the sensing elements, logic circuits, or other downstream circuitry receive only defined digital values.
According to the present invention, corruption prevention circuits are used to force a read bit line to a known digital value by discharging the read bit line when a cell structure is being written to at the same time a read is performed on the corresponding read word line. Consequently, according to the present invention, the value on the read bit line is forced to a known digital value by the corruption prevention circuit of the invention and the prior art problem of the value being read having an unknown or indeterminate value that is neither a digital low nor a digital high is eliminated. Therefore, using the method and structure of the invention, indeterminate values are never propagated down stream to the sensing elements, logic elements, or other downstream circuitry of the system and there is no potential failure of the downstream circuitry.
According to the present invention, corruption prevention circuits are specifically designed to be operatively coupled to the existing write word lines. Since write word lines are already required, there is minimal new structure added. In addition, the corruption prevention circuits of the invention can be placed physically very close to read bit lines, in one embodiment on the order of five to ten microns from the edge of the array. This means that the addition of the corruption prevention circuits of the invention results in minimal additional capacitance and the size of the resulting improved rotated-read memory structure can be kept almost the same as prior art structures.
In addition, the transistors used in the corruption prevention circuits of the invention can be sized very small without adversely effecting the down stream timing, and, in some embodiments of the invention, the addition of corruption prevention circuits of the invention allows for additional delay times by either sizing the corruption prevention circuit components appropriately or by adding well known delay elements to the corruption prevention circuits of the invention.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.